The present invention relates generally to a semiconductor device and, more particularly, to a circuit and a method for shifting an address.
Semiconductor memory devices are provided with a circuit for shifting an input by a predetermined time from a clock signal CLK to fit to an operation timing of commands, such as a reading command or a write command.
FIG. 1 is a block diagram of a circuit for shifting an address 10 according to the related art.
As shown in FIG. 1, the circuit for shifting an address 10 according to the related art is composed of a plurality of flip-flops 11, which is a shift register structure.
The flip-flops 11 disposed at the foremost stage receive address signals A0˜An in response to a reading command RD or a write command WT and the next flip-flops 11 output shifted address signals A0_n˜An_n by sequentially shifting the address signals A0˜An in response to a clock signal CLK.
FIG. 2 is a circuit diagram of the flip-flop 11 of FIG. 1.
As shown in FIG. 2, the flip-flop 11 can be composed of a plurality of inverters IV1˜IV5 and a plurality of pass gates PG1, PG2.
The flip-flop 11 is configured to latch an input signal D in a low-level period of a clock signal CLK and output the latched signal as an output signal Q in a high-level period of the clock signal CLK. The flip-flop 11 has a 2-stage structure that operates in the low-level period and the high-level period of the clock signal CLK.
A conventional circuit for shifting an address with the above structure are problematic.
All of the flip-flops 11 in conventional circuits for shifting an address operate in response to a clock signal CLK. Therefore, in the address shifting operation, all the flip-flops 11 operate every time a clock signal CLK toggles (other than flip-flop that outputs an address signal fitting a timing for the actual operation), thereby causing unnecessary consumption of electric current.
As shown in FIG. 2, conventional circuits for shifting an address have the flip-flop 11 with a 2-stage structure that performs latching and outputting in the high-level period and a low-level period of a clock signal CLK, thereby increasing the circuit area.